EEPROM devices are well known in the prior art and may be categorized broadly into two groups: those memory arrays which employ memory cells utilizing a single transistor and those memory arrays which employ memory cells which utilize two transistors. The advantage in utilizing two transistors per memory cell is that a differential output signal may be obtained which can be sensed by a differential sense amplifier, providing greater speed of operation and less susceptibility to errors caused by noise. However, utilizing two transistors per memory cell consumes a greater amount of surface area in an integrated circuit than memory devices utilizing a single transistor per memory cell.
FIG. 1 depicts a schematic diagram of a memory device utilizing an array of two transistor memory cells and a differential sense amplifier. For convenience, only a single memory cell formed of transistors 11 and 12 is shown, although it is well known in the art how such memory arrays comprising a plurality of memory cells, each containing two transistors, are formed and selectively addressed. Referring to FIG. 1, floating gate transistors 11 and 12 each include a floating gate which is selectively charged to increase the control gate threshold voltage of the transistor to correspond to a logical zero, as compared with the control gate threshold voltage of a transistor having substantially no charge placed on its floating gate and corresponding to a logical one. In circuit 10 of FIG. 1, transistors 11 and 12 are erased to be in the low threshold voltage state, i.e., each having a threshold voltage corresponding to a logical one. Then, during programming, either transistor 11 or 12 is programmed by placing a charge on its floating gate in order to increase its threshold voltage to correspond to a logical zero, thereby providing a differential data signal on BIT and BITlines 18 and 19, which is in turn applied to the differential input leads of differential sense amplifier 20. Differential sense amplifier 20 in turn provides a single ended output signal on output terminal 21 which is capable of being provided more quickly and with less susceptibility to noise and variations of voltage levels on leads 18 and 19 than is possible if a single input sense amplifier were used, as depicted in the prior art structure of FIG. 2. Table 1 depicts the operation of memory cell 10 shown in FIG. 1 during the erase and programming modes.
TABLE 1 ______________________________________ StateProgrammed V.sub.T Transistor 11 ##STR1## V.sub.T Transistor 12 BIT ______________________________________ erased low 1 low 1 0 low 1 high 0 1 high 0 low 1 ______________________________________
As shown in FIG. 2, another type of memory array is constructed of a plurality of memory cells, each containing a single floating gate transistor, such as transistor 31. Again, for simplicity, the entire array of memory cells is not shown, such construction being well known to those of ordinary skill in the art. During reading of a selected memory cell, BIT line 35 is connected to the input lead of single input sense amplifier 37. Sense amplifier 37 is inherently slower (due to its responding to a non-differential input signal which changes voltage in one direction with respect to a reference voltage) and more susceptible to noise and variations in voltage levels on BIT line 35 (due to its lack of common mode noise rejection) than is the differential sense amplifier 20 of FIG. 1 having its input leads connected to both BIT and BITlines.
The prior art circuit of FIG. 3 has combined the use of a memory array having a plurality of memory cells, each containing a single floating gate transistor, with the higher speed and lower susceptibility to noise of a differential sense amplifier. For simplicity, FIG. 3 shows only a single memory cell formed of transistor 101-N-1 associated with row line 102-N and BIT line 103-1. It is readily understood by those of ordinary skill in the art that the memory array actually includes a plurality of N row lines and M BIT lines, and a plurality of N.times.M uniquely addressable single transistor memory cells.
When transistor 101-N-1 is selected for reading, row line 102-N is enabled by placing a read voltage having a voltage greater than the control gate threshold voltage of a memory array transistor which is programmed to the logical one state (no charge on its floating gate), and less than the control gate threshold voltage of a memory array transistor which is programmed to a logical zero state (a charge placed on its floating gate). BIT line 103-1 is selected by turning on column select transistors 104-1 and 105-1 and applying reference voltage VREF to the gate of transistor 106-1. As shown in FIG. 3, transistors 104-1 and 105-1 serve as column select transistors connected in an AND configuration. Other addressing techniques or the use of other than two select transistors 104-1, 105-1, are well known in the art. The reference voltage applied to the gate of transistor 106-1 is approximately 2.5 to 3 volts and causes transistor 106-1 to precharge the selected column 103-1. When memory array transistor 101-N-1 stores a logical one, it turns on when selected for reading, causing differential sense amplifier input lead 107 to be connected to ground. Conversely, when memory array transistor 101-N-1 stores a logical zero it does not turn on when selected for reading due to its higher control gate threshold voltage. In this case, input lead 107 of differential sense amplifier 111 is not connected to ground, and the current I/2 supplied by array load current source 109 is not discharged to ground but is made available on high impedance input lead 107 of differential sense amplifier 111.
Although not shown in FIG. 3, it is well known in the art that various multiplexing techniques can be used to multiplex a plurality of columns to a single differential sense amplifier, or to multiplex a plurality of output leads from a plurality of differential sense amplifiers to a single output lead of an integrated circuit.
In order to provide a differential input signal to differential sense amplifier 111, a set 117 of reference transistors is provided between differential input lead 108 and ground in the same configuration as those elements located between differential input lead 107 and ground. Thus, reference set 117 includes a reference unprogrammed memory cell 101-N-REF (storing a logical one) and having its control gate connected to row line 102-N. Similarly, reference set 117 includes reference transistors 104-REF and 105-REF corresponding to column select transistors 104-1 and 105-1, respectively, with their control gates connected to VCC (typically 5 volts). Reference set 117 also includes transistor 106-REF having its control gate connected to reference voltage VREF, serving as an analog to transistor 106-1. Reference load current source 110 provides a current I equal to twice the current provided by array load current source 109.
Balancing transistor 118 serves to connect the inverting and noninverting input leads of differential sense amplifier 111 prior to sensing the data stored in the selected memory cell. As shown in FIG. 3, balancing transistor 118 is a P channel transistor controlled by a signal BALapplied to its gate electrode which goes high when sensing is to be performed following selection of a desired row and column defining the single memory cell to be sensed by differential sense amplifier 111.
When memory array transistor 101-N-1 stores a logical zero and is selected for reading, differential input lead 107 is not connected to ground and thus when balancing is terminated (i.e., when transistor 118 turns off): ##EQU1## where .DELTA.V.sub.107 =the rate of change of the voltage on differential input lead 107;
V.sub.108 =the constant reference voltage to be compared to the voltage of sense node 107; PA1 I=The reference current through reference Bit line 103-REF; PA1 .DELTA.t=a change in time; PA1 C.sub.107 =the capacitance on input lead 107; and PA1 dv/dt=the time rate of change of the differential input voltage between differential input leads 107 and 108.
Conversely, when memory array transistor 101-N-1 stores a logical one and is selected for reading ##EQU2##
Unfortunately, the rate of change of differential input voltage in the prior art circuit of FIG. 3 is only one half that developed by a prior art circuit, such as shown in FIG. 1, which utilizes two transistors per memory cell. Thus, the prior art circuit of FIG. 3 is slower than a prior art circuit which utilizes two transistors per memory cell.